/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2023-2023. All rights reserved.
 */

#ifndef NIC_MIG_MPU_INTF_H
#define NIC_MIG_MPU_INTF_H

#include "nic_mpu_cmd_defs.h"

#ifndef MAX_CEQ_PER_FUNC
#define MAX_CEQ_PER_FUNC 0x20
#endif

#define MAX_INTR_NUM 0x80
#define MIG_FUNC_TBL_SIZE 0x50
#define MIG_VAT_TBL_SIZE 0x10
#define SQ_CI_ATTR_SIZE 0x14
#define MAX_CMDQ_NUM 0x4
#define CMDQ_CTX_SIZE 16
#define MAX_SQ_NUM 0x20
#define MAX_RQ_NUM 0x20
#define RSS_KEY_SIZE 0x28
#define RSS_INDIR_TBL_SIZE 0x200

struct mig_nic_set_ceq_ctrl {
    struct hinic3_mgmt_msg_head head;
    u16 func_id;
    u8 ceq_num;
    u8 rsvd;
    u32 ceq_ctrl0[MAX_CEQ_PER_FUNC];
    u32 ceq_ctrl1[MAX_CEQ_PER_FUNC];
};

/* the only ctrl csr need to be mig is CTRL0 and CTRL4 */
struct mig_nic_msix_info_rw {
    struct hinic3_mgmt_msg_head head;
    u16 func_id;
    u8 intr_num;
    u8 msi_ctl_csr_op;
    u32 msix_ctrl0[MAX_INTR_NUM];
    u32 msix_ctrl4[MAX_INTR_NUM];
};

struct mig_nic_func_vat_tbl {
    struct hinic3_mgmt_msg_head head;
    u16 func_id;
    u8 opcode;
    u8 rsvd;
    u8 func_tbl[MIG_FUNC_TBL_SIZE];
    u8 vat_tbl[MIG_VAT_TBL_SIZE];
};

struct mig_nic_vf_info {
    u8 sq_num;
    u8 rq_num;
    u8 cmdq_num;
    u8 cmdq_depth;
    u16 rq_depth;
    u16 sq_depth;
    u32 sq_ci_base_addr_h;
    u32 sq_ci_base_addr_l;
    u64 cmdq_cla_addr[MAX_CMDQ_NUM];
};

struct mig_nic_func_cfg {
    struct hinic3_mgmt_msg_head head;
    u16 func_id;
    u16 rsvd;
    struct mig_nic_vf_info vf_info;
};

struct mig_nic_chk_mbx_empty {
    struct hinic3_mgmt_msg_head head;
};

struct mig_nic_vport_state {
    struct mgmt_msg_head msg_head;
    u16 func_id;
    u16 rsvd1;
    u8 state;  /* 0--disable, 1--enable */
    u8 rsvd2[3];
};

struct mig_nic_single_sq_ci {
    u8 sq_ci_attr[SQ_CI_ATTR_SIZE];
    u32 rsvd;
    u64 sq_ci_tbl;
};

struct mig_nic_sq_ci {
    struct mgmt_msg_head msg_head;
    u16 func_id;
    u8 opcode;
    u8 sq_num;
    struct mig_nic_single_sq_ci sq_ci[MAX_SQ_NUM];
};

struct mig_nic_rss_tbl {
    u8 rss_enable;
    u8 rss_hash_engine;
    u16 rsvd;
    u32 rss_ctx;
    u8 rss_indri_tbl[RSS_INDIR_TBL_SIZE];
    u8 rss_key[RSS_KEY_SIZE];
};

struct mig_nic_rss_tbl_cfg {
    struct mgmt_msg_head msg_head;
    u16 func_id;
    u8 opcode;
    u8 rsvd;
    struct mig_nic_rss_tbl rss_tbl;
};

struct mig_nic_mac_vlan {
    u8 mac[ETH_ALEN];
    u8 rsvd1[2];
    u16 vlan_id;
    u16 rsvd2;
};

struct mig_nic_cfg_mac_tbl {
    struct mgmt_msg_head msg_head;
    u16 func_id;
    u8 opcode;
    u8 rsvd;
    struct mig_nic_mac_vlan mac_vlan_tbl;
};

struct mig_nic_tmp_cfg_cmdq_ctx {
    struct mgmt_msg_head msg_head;
    u16 func_id;
    u16 rsvd;
    u8 cmdq_ctx[CMDQ_CTX_SIZE * MAX_CMDQ_NUM];
};

#endif